Результаты вычислительных экспериментов

Рисунок ПБ.1 - Продолжение

void

DMA1_Stream3_Chanel4_Configuration(void

)

{DMA_DeInit (DMA1_Stream3);_struct. DMA_Channel = DMA_Channel_4;_struct. DMA_PeripheralBaseAddr = (uint32_t) (&USART3->DR);_struct. DMA_Memory0BaseAddr = (uint32_t) buffer;_struct. DMA_DIR = DMA_DIR_MemoryToPeripheral;_struct. DMA_BufferSize = sizeof(buffer);_struct. DMA_PeripheralInc = DMA_PeripheralInc_Disable;_struct. DMA_MemoryInc = DMA_MemoryInc_Enable;_struct. DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;_struct. DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;_struct. DMA_Mode = DMA_Mode_Normal;_struct. DMA_Priority = DMA_Priority_High;_struct. DMA_FIFOMode = DMA_FIFOMode_Disable;_struct. DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull;_struct. DMA_MemoryBurst = DMA_MemoryBurst_Single;_struct. DMA_PeripheralBurst = DMA_PeripheralBurst_Single;_Init (DMA1_Stream3, &dma1_struct);_Cmd (DMA1_Stream3, ENABLE); }

void

DMA1_Stream1_Chanel4_Configuration(void

)

{DMA_DeInit (DMA1_Stream1);_struct. DMA_Channel = DMA_Channel_4;_struct. DMA_PeripheralBaseAddr = (uint32_t) (&USART3->DR);_struct. DMA_Memory0BaseAddr = (uint32_t) recived_data;_struct. DMA_DIR = DMA_DIR_PeripheralToMemory;_struct. DMA_BufferSize = sizeof

(recived_data);_struct. DMA_PeripheralInc = DMA_PeripheralInc_Disable;_struct. DMA_MemoryInc = DMA_MemoryInc_Enable;_struct. DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;_struct. DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;_struct. DMA_Mode = DMA_Mode_Circular;_struct. DMA_Priority = DMA_Priority_High;_struct. DMA_FIFOMode = DMA_FIFOMode_Disable;_struct. DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull;_struct. DMA_MemoryBurst = DMA_MemoryBurst_Single;_struct. DMA_PeripheralBurst = DMA_PeripheralBurst_Single;_Init (DMA1_Stream1, &dma1_struct);_EnableIRQ (DMA1_Stream1_IRQn);_ITConfig (DMA1_Stream1, DMA_IT_TC, ENABLE);_Cmd (DMA1_Stream1, ENABLE); }

int

main

(void

)

{RCC_Configuration ();_Configuration ();_Snapshot_Configuration ();_Adc_Configuration (9600);_SelectOutputTrigger (TIM2, TIM_TRGOSource_Update);_Dac_Configuration (3000);_Configuration ();_Stream1_Chanel4_Configuration ();_Configuration ();_Stream6_Chanel7_Configuration ();_Chanel2_Configuration ();

while

(1) {} }

void

DMA1_Stream1_IRQHandler(void

)

{

if

(DMA_GetITStatus (DMA1_Stream1, DMA_IT_TCIF1)! = RESET)

{ switch

(recived_data [0])

{

case

('1'):

{

switch

(recived_data [1])

{case

('1'):

{_RegularChannelConfig (ADC1, ADC_Channel_0, 1, ADC_SampleTime_3Cycles); // total conv. time = 3+8 = 11cycle at 36MHz (ADC freq.) = 0.305 uS

break

; // 3 278 688 Hz

}

Рисунок ПБ.1 - Продолжение

case

('2'):

{_RegularChannelConfig (ADC1, ADC_Channel_0, 1, ADC_SampleTime_15Cycles); // total conv. time = 15+8 = 23cycle at 36MHz (ADC freq.) = 0.638 uS

break

;

}

case

('3'):

{_RegularChannelConfig (ADC1, ADC_Channel_0, 1, ADC_SampleTime_28Cycles); // total conv. time = 28+8 = 36cycle at 36MHz (ADC freq.) = 1 uS

break

;

}

case

('4'):

{_RegularChannelConfig (ADC1, ADC_Channel_0, 1, ADC_SampleTime_56Cycles); // total conv. time = 56+8 = 64cycle at 36MHz (ADC freq.) = 1.7 uS

break

;

}

case

('5'):

{_RegularChannelConfig (ADC1, ADC_Channel_0, 1, ADC_SampleTime_84Cycles); // total conv. time = 84+8 = 92cycle at 36MHz (ADC freq.) = 2.5 uS

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